Job Description

  • Work closely with the analog, custom digital, and NVM design teams for the development of test benches and regression suites for verification purposes
  • Write verification plans and create automated testbenches
  • Experience developing behavioral models for custom IP (System Verilog-RNM, VerilogA/AMS, wreal) and work with the digital design teams to ensure proper integration
  • Experience and expert knowledge of automation and development of new tests and create regression flows
  • MSEE with several years of industry experience in mixed-signal verification
  • Experience with the following: mixed-signal design, Co-simulation (analog and digital), Mixed-signal verification methodologies
  • Thorough understanding of AMS simulations, digital RTL, analog schematics
  • Background in verification languages and methodologies (Verilog, VerilogA/AMS, SV-RNM, UVM, etc.)
  • Solid programming background (Python, ruby, etc.)
  • Familiarity with common EDA tools (Virtuoso, NCVerilog, Spectre, etc.)

Application Instructions

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