Job Description

Minimum requirements:

  • BSEE, Computer Engineer or comparable and 2+ years of experience
  • Experienced with verification methodology such as UVM/VMM/OVM.
  • Developed test plans of complex systems containing multiple state machines and protocol rules.
  • Composed functional coverage assertions, preferably using System Verilog. Preferred candidate will possess the following:
  • Exposure to either CPU coherency protocols or DDR memory controllers.
  • ARM-ACE Coherency or LPDDR4/5 experience would be a bonus.
  • Proficient in System Verilog, C++, and Python/Perl scripting
  • Excellent verbal and written communication skills. 
 

Application Instructions

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