Job Description

Design Verification Engineer
Austin, TX
6-12 month Contract

• 4-10 years industry experience
• Development of UVM test benches
• Creation of test stimulus
• Debug of test results
• Creation of automation tools
• Testing for design performance
• Strong knowledge of computer architecture
• Strong knowledge of Verification Methodologies
• Strong Understanding and experience with Verilog, SV, and UVM

Application Instructions

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