Job Description

DV Engineer
San Jose, CA
Contract to Hire preferred

*Create and enhance constrained-random verification environments using SystemVerilog and UVM

• 8+ years or more of practical semiconductor design verification experience including System Verilog, UVM, assertions and coverage driven verification.
• Experience using multiple verification platforms: UVM test bench, emulator, software environments and system testing
• Experience with test plan development, building the necessary test bench infrastructure, developing tests and verifying the design
• Experience with identifying bugs in architecture, functionality and performance issues
• Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing
• Experience with scripting languages (Python or Perl) for automation
• Object-oriented programming concepts required
• Experience with C/C++
• Audio/Video, HDMI, USB, Display Port a big + but not a hard requirement

Application Instructions

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