Job Description


Digital ASIC Design Engineer
Beaverton, OR
FTE/PERM

Requirements:
• System Architecture and Verilog RTL design
• Writing system architecture specifications
• Translating functional specifications into design requirements
• Knowledge of audio DSP methods a definite plus
• Experience with embedded processors and various serial data interfaces a plus
• Design-for-test methods
• Verilog
• Verification
• Test bench creation and use
• Low power implementation techniques
• Experience with clock systems and multiple asynchronous clock domains

Additional Skills:
• Formal Analysis/Logical Equivalence Checking
• Post layout verification including gate level simulation
• Power estimation
• Clock Domain Crossing Analysis
• Pre-purchase analysis of complex IP blocks, and IP integration and evaluation
• Design of bus functional simulation models
• System Verilog
• Python, Perl, TCL

Application Instructions

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