Job Description

Req2944
Digital Design Verification Engineer
Austin, TX
6-12 month Contract

• Development of UVM testbenches
• Creation of test stimulus
• Debug of test results
• Creation of automation tools
• Testing for design performance
• 4-10 years industry experience
• Strong knowledge of computer architecture
• Strong knowledge of Verification Methodologies
• Strong Understanding and experience with Verilog, SV, and UVM
• BS/MS in EE, CE or CS

Thanks and Regards
Venu Keshav
ASICSoft
650-249-6240
venu@asicsoft.com
https://www.linkedin.com/in/venu-r-keshav-549a97126

Application Instructions

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