Job Description

  • SystemVerilog and UVM for verifying complex ASIC/FPGA
  • Software driven test development using SystemVerilog and UVM.
  • SystemVerilog Assertions and Functional Coverage development for hardware requirement and interface protocol checks.
  • Development of models using SystemC, C/C++, Python, Matlab
  • Use / Develop Verification IP (VIP) for verification
  • ARM based UVM verification
  • Automation with Scripts: regressions, Make files, project setup, Python and C/C++,┬áRevision control

Required Skills

  • Strong logical and creative problem-solving skills with excellent analytical and debugging skills
  • Must be a flexible self-starter who can ramp up with new technologies, products, etc.
  • Motivated, and able to work effectively under pressure
  • Good written and oral communication skills
  • MS or Ph. D. grad in CS/EE

Application Instructions

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