Job Description

Req#2912
FPGA Design Verification Engineer
San Jose, CA
6-12 Month Contract

Job Description:
About 7+ years FPGA RTL Design and verification experience
Knowledge of UVM or OVM Verification framework/methodology is required
Knowledge of Ethernet, PCIE, AXI, I2C, MDIO buses is a must
Familiarity with FPGA design methodology with Altera or Xilinx architecture is a must
Knowledge of Verilog, System Verilog for RTL design required
Knowledge of Tcl/PERL/Python or other scripting tools preferred
Ability to do lab debug and use lab equipment is highly desired
Write tests cases and validate functionality of FPGAs
Develop regression environment and track functional coverage

Thanks and Regards
Venu Keshav
ASICSoft
650-249-6240
venu@asicsoft.com
https://www.linkedin.com/in/venu-r-keshav-549a97126

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