Job Description

Title: Sr. FPGA Verification Engineer

Type: 12+ month contract

Location: Fremont, CA

Project Info:

Senior FPGA Design Verification engineer experienced with developing Test Bench infrastructures from the ground up.
  • 7-10+ years FPGA/ASIC Design Verification
  • Extensive Test Bench Development
  • Expert with SystemVerilog
  • Expert with UVM 
  • Block and full-chip level test bench
  • Xilinx Virtex, desired

Application Instructions

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