Job Description

Physical Design Engineer
Austin, TX
6 – 12 months

**Must have 5+ years of experience in synthesis through closure (sign off)

Job Requirements:
• MSEE or BSEE with 5+ years relevant experience preferred (or equivalent education and experience)
• Synopsys DC/ICC2, Fusion Compiler knowledge is required.
• Strong communication skills, team player working in collaborative work environment, discipline and planning; ability to execute with high quality deliverables is a must
• Solid understanding and working knowledge of the GPU/ASIC design flow with solid experience in taping out designs
• Experience with 16nm finfet or smaller process nodes is strongly preferred
• Hands-on experience with synthesis, block and full chip implementation with the latest industry P&R/STA flows and tools
• Solid hands on experience with clock tree synthesis (CTS), multi-voltage and multi-clock designs
• Strong working knowledge of formal equivalency checks, LP checks, timing constraints, UPF.
• Experience in block level floor-planning, implementing power grid and area/congestion optimization

Job Responsibilities:
• Hands-on responsibility from synthesis to place and route of a complex GPU block through signoff flows including timing and physical verification
• Synthesis, Floor plan, Place & Route in chip-level and hierarchical physical implementation environment
• Running MBIST and DFT insertion into block, understanding impact of MBIST/Scan and debug logic is desirable
• Interact with RTL counterpart to resolve design issues pertaining to block closure
• Ability to work independently to make good technical trade-offs between power, area, timing
• Ability to work well in a team setting
• Assist design leads to own and drive critical design issues to closure.

Application Instructions

Please click on the link below to apply for this position. A new window will open and direct you to apply at our corporate careers page. We look forward to hearing from you!

Apply Online