Job Description



RTL Design Engineer
Irvine, CA/ San Jose, CA
Contract & Full Time

“This need is for an experienced ASIC PCIE/CXL RTL designer
Looking for an ASIC RTL designer who has experience working on PCIE Endpoint IP integration and debug.
Preferably with experience/ familiarity with using Synopsys PCIe IP

Position Requirements:
• Must have 5+ years of experience in RTL level ASIC design, including use of a source control system and be able to debug RTL code using simulation tools
• PCIE Gen4/ 5 protocol understanding and experience
• Must be expert in Verilog, System Verilog and proficient in verification, timing analysis and optimization.
• Familiarity with Synthesis, STA and Design Audit tools like Spyglass

Application Instructions

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