Job Description

LOCATION: Fremont OR San Francisco, CA (onsite req'd)

DURATION: 3-4+ Months (possibility of conversion)

TITLE: Physical Design Engineer

Client is looking for a strong Physical Design Engineer who can take a block from Netlist to GDSII and handoff to top level integration. The current design is at 65nm TSMC and will be moving to 28nm TSMC. This is an opportunity to work for a hot startup working on cutting edge neural interface chips. Candidate can work from either the Fremont or SF location but will be expected to attend a meeting in SF every week or two. 

  • Block Level Physical Design
  • Experience with Synthesis
  • Experience Synopsys toolflow and tools (Design Compiler, ICC2, PrimeTime)
  • 65nm/28nm TSMC Process experience
  • Experience modifying design flows from one node size to another
  • TCL scripting experience
  • Experience with taking a block from Netlist to GDSII handoff
  • 5-10+ years experience

Application Instructions

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