Job Description

  • Expert level with Verilog RTL
  • Experience with back-end tools (Lint, LEC, Synthesis, CDC, STA, PnR, etc.)
  • Experience with writing Verilog test benches ? Knowledge of scripting tools and Unix command-line environment
  • Experience with Cadence Virtuoso
  • Familiarity with micro-controller implementations
  • Experience with Cadence AMS Simulator and analog modeling important for this role
  • Experience with Analog mixed-signal design flows
  • Proficiency in programming (tcl, python, etc.)
  • FPGA prototyping experience
  • Experience in Lab prototype evaluation methods
  • Conversion of high-level system specification to RTL/Verilog modules
  • Bachelor’s in electrical engineering and 7+ years of industry experience

Application Instructions

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