Job Description


Sr. FPGA Design Engineer
San Jose, CA
6 -10 months +

Requirements
• FPGA architecture, IP selection, IP evaluation, IP integration, FPGA building, timing closure, and debugging with chipscope.
• Design top-level block designs in Vivado and integrate customized RTL IPs.
• Create key IPs, implement prototypes, evaluate and integrate acquired hardware Intellectual Property (IP).
• Work with other hardware/ software architects developing one-of-a-kind innovative FPGA prototypes and contribute to feasibility studies & developing solutions.

REQUIRED SKILLS
• B.S., M.S., or Ph.D. in Computer Engineering or Electrical Engineering with 5-10 years of industry experience.
• Demonstrated ability with FPGA design tool flows, synthesis, timing analysis, partitioning, FPGA programming, bring up and testing.
• In-depth background in high-speed logic design, Verilog, top-level integration, synthesis, debug, Tcl, shell scripts (Synopsys, Xilinx, or FPGA tools).
• Experience with integration of PCIE, DDR, AXI 3rd party IP in an FPGA environment.
• Prior experience with system-level testing, lab validation, chipscope debugging.
• Must be highly motivated with excellent organization and communication skills.
• Knowledge of processor design, accelerators, and/or memory hierarchies.
• Experience in Verilog/TCL/Shell programming and scripting in a Linux environment.
• Knowledge of high-performance design techniques.
***FPGA designer for NMT to help us with Xilinix FPGA build and support chipscope lab debug in the lab.
*** Must have Xilinx toolchain/Vivado/timing closure/chipscope.

Thanks and Regards
Venu Keshav
ASICSoft
650-249-6240
venu@asicsoft.com
https://www.linkedin.com/in/venu-r-keshav-549a97126

Application Instructions

Please click on the link below to apply for this position. A new window will open and direct you to apply at our corporate careers page. We look forward to hearing from you!

Apply Online