Job Description

Hi

 

I am Himanshu from AsicSoft! I came across your resume in regards to the below job reference.  Please reply with your updated copy of resume as response or call me at to know more about it!

 

Title: RTL Design Engineer

Location: Carlsbad, CA

Duration: 06- 12 month

Position Requirements:

  • Must have 5+ years of experience in RTL level ASIC design, including use of a source control system and be able to debug RTL code using simulation tools
  • Prototype lab bring up and silicon validation experience for at least one device
  • Datapath / Packet processing experience 
  • DMA/ Datapath design experience
  • PCIE Gen4/ 5 protocol understanding and experience
  • Compression/decompression and encryption/decryption experience is a plus.
  • Must be expert in Verilog, System Verilog and proficient in verification, timing analysis and optimization. Be able to work in Linux and Windows environments
  • Familiarity with Synthesis, STA and Design Audit tools like Spyglass
  • UVM familiarity is desirable
  • Low power design techniques and tool scripting (e.g. Perl) is a plus.
  • Solid knowledge of computer architecture and circuit issues/analysis is a bonus, though a basic working knowledge of these areas is essential.
  • Strong analytical thinking and problem-solving skills, excellent attention to detail, and good coding skills and style required.
  • Must have good English hearing, speaking, reading, and writing capabilities.

Must have good teamwork and interpersonal skills

 

Application Instructions

Please click on the link below to apply for this position. A new window will open and direct you to apply at our corporate careers page. We look forward to hearing from you!

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