Job Description

Sr. RTL Engineer
San Jose, CA
Contract to Hire Preferred

• Experienced in Verilog, SystemVerilog & VHDL
• Engineer will be responsible for the micro-architecture, RTL implementations, simulations and trial synthesis
• Expert with digital simulations tools
• Must know micro-controller implementation flows
• Strong Knowledge of back-end tools (Lint, LEC, Synthesis, CDC, STA, PnR, etc.)
• Knowledge with Verilog test benches and UVM environment
• Responsibility for the design, simulations and integration video IPs. HDMI and USB experience along with Serdes knowledge a big +

Application Instructions

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