Job Description

  • Experienced in Verilog, SystemVerilog & VHDL
  • Engineer will be responsible for the micro-architecture, RTL implementations, simulations and trial synthesis
  • Expert with digital simulations tools 
  • Must know micro-controller implementation flows
  • Strong Knowledge of back-end tools (Lint, LEC, Synthesis, CDC, STA, PnR, etc.)
  • Knowledge with Verilog test benches and UVM environment
  • Responsibility for the design, simulations and integration video IPs.  HDMI and USB experience along with Serdes knowledge a big +
  • Bachelor’s in electrical engineering or computer science and 10+ yrs of experience
 

Application Instructions

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